In order to incorporate more functions and achieve better performance and less cost, integrated circuits are formed with increasingly smaller dimensions. However, there are legacy circuits that have already been designed with greater dimensions. It is not cost effective to redesign these circuits for smaller dimensions, and these circuits were typically shrunk before they are implemented on silicon wafers. Conventionally, foundries performed the task of shrinking integrated circuits.
Since the performances of integrated circuits are often related to their sizes, some integrated circuits are preferably not shrunk. For example, analog circuits and some high-speed integrated circuits need to keep their original sizes in order to maintain their performance unchanged throughout different generations of integrated circuits. This creates a dilemma. Since these non-shrinkable integrated circuits are often integrated in the same semiconductor chips with shrinkable integrated circuits, whose performances are not affected by their dimensions, the integrated circuits for a semiconductor chip cannot be uniformly shrunk, and efforts are needed to shrink only the shrinkable circuits, while keeping the non-shrinkable circuits intact.
To achieve this goal, typically, the graphic data system (GDS or GDSII format) layout of the non-shrinkable circuits was blown up (magnified) first. An abstract is then generated from the blown-up GDS layout of the non-shrinkable circuits. The blown-up GDS layout and the respective abstract are then merged with the GDS layout and the abstract of shrinkable circuit layouts to generate a new integrated circuit. Foundries can then shrink the new integrated circuit to substantially a same scale as the GDS layout of the non-shrinkable circuit was magnified. Accordingly, the GDS layout of the non-shrinkable circuits is restored back to the original size, while the shrinkable circuits are shrunk.
The conventional methods for shrinking integrated circuits suffer drawbacks, however. First, even if the non-shrinkable circuits are magnified and then shrunk in a same scale, the resulting dimensions and locations of the final circuits may not be exactly the same as in the original design. This is due to the snapping of integrated circuits to grids, which causes the change in the size and/or location of integrated circuit components. The change in dimensions may cause performance drift. Second, GDS files are typically hierarchical with a plurality of levels. In order to avoid the adverse generation of broken lines caused by snapping, the hierarchy of GDS files needs to be flattened into a same level, resulting in a big GDS file. This causes the handling time to be longer. Third, the adverse change in the dimensions of integrated circuits due to the snapping causes device mismatching. For matching devices, even though they have exactly the same dimensions as that of before the shrinking process, but since they are at different locations, after shrinking, they may have different sizes. Therefore, the performance matching is broken.
What is needed in the art, therefore, are new methods for shrinking integrated circuits without causing the above-discussed problems.